`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:26:18 12/07/2011 
// Design Name: 
// Module Name:    SevenSeg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

//
module SevenSeg(clk, an, cath);
	input wire clk;	
	output reg [0:3] an;
	output reg [0:7] cath;

//module SevenSeg(clk);
//	input wire clk;	
//	reg [0:3] an;
//	reg [0:7] cath;

	//make my own disp_clock that runs at ~60Hz
	reg disp_clk;
	
	initial begin
		disp_clk = 0;
	end
	
	reg [15:0] disp_cnt;
	initial begin
		disp_cnt = 0;
	end
	
	always @ (clk)
	begin
		if (disp_cnt == 16'b1111111111111111) begin
			disp_clk = ~disp_clk;
			disp_cnt = 0;
		end else begin
			disp_cnt = disp_cnt + 1;
		end
	end

	reg [2:0] value;


	wire [1:0] digitloc;
	wire digitval;
	Display3BitVal CycleDigits(disp_clk, value, digitloc, digitval);
	
	
	wire [0:3] enable;
	wire [0:7] cathval;
	
   DisplayDigit DisplayDigitInst(.digit (digitloc),
											.val (digitval), 
											.digitEnable (enable),
											.ssvalue (cathval)
											);
	initial begin
		value = 6;
	end
 

	always @ (posedge disp_clk) begin
		an[0:3] = enable;
		cath[0:7] = cathval;
	end

//		begin
//			if (counter == 4) begin 
//				counter = 0;
//			end else begin
//				counter = counter + 1;
//			end
//		end
//	end
	
endmodule //bitsToSseg

module Display3BitVal(disp_clk, numbers, digitloc, digitvalue);
	input wire disp_clk;
	input wire [0:2] numbers;
	output reg [1:0] digitloc;
	output reg digitvalue;
	
	//cycle through the digits to display
	//cycle through the bit (1 or 0) to display
	initial digitloc = 3;
	
	always @ (posedge disp_clk)
		begin
			if (digitloc > 1) begin
				digitloc = 0;
				digitvalue = numbers[digitloc];
			end else begin 
				digitloc = digitloc + 1;
				digitvalue = numbers[digitloc];
			end
		end
			
endmodule
			
	

module DisplayDigit(digit, val, digitEnable, ssvalue);
	input wire [1:0] digit; //which digit?
	input wire val;  //display a 1 or 0?
	output [0:3] digitEnable;
	output [0:7] ssvalue;

	reg [0:3] digitEnable; 
	reg [0:7] ssvalue;	
		
	always @ (val)
	begin
		case(val)
			0 : ssvalue = 8'b00000011;
			1 : ssvalue = 8'b10011111;
			default : ssvalue = 8'b11111100;
		endcase
	end
	
	always @ (digit)
	begin 
		case(digit)
			0 : digitEnable = 4'b1110;
			1 : digitEnable = 4'b1101;
			2 : digitEnable = 4'b1011;
			3 : digitEnable = 4'b0111;
			default : digitEnable = 4'b1111;
		endcase
	end
	
endmodule //DisplayDigit

//module TestSS;
//    reg clock;
//    initial clock = 1;
//	 
//    always 
//		#10000 clock = ~clock;
//
//	 SevenSeg UUT(clock);
//	
//endmodule
